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RT8279 1 ds8279-01 december 2011 www.richtek.com ordering information pin configurations (top view) note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. applications z distributive power systems z battery charger z dsl modems z pre-regulator for linear regulators sop-8 (exposed pad) 5a, 36v, 500khz step-down converter general description the RT8279 is a step-down regulator with an internal power mosfet. it achieves 5a of continuous output current over a wide input supply range with excellent load and line regulation. current mode operation provides fast transient response and eases loop stabilization. for protection, the RT8279 provides cycle-by-cycle current limiting and thermal shutdown protection. an adjustable soft-start reduces the stress on the input source at startup. in shutdown mode, the regulator draws only 25 a of supply current. the RT8279 requires a minimum number of readily available external components, providing a compact solution. the RT8279 is available in the sop-8 (exposed pad) package. sw boot nc fb nc en vin gnd 2 3 4 5 8 7 6 gnd 9 features z z z z z 5a output current z z z z z internal soft-start z z z z z 110m internal power mosfet switch z z z z z internal compensation minimizes external parts count z z z z z high efficiency up to 90% z z z z z 25 a shutdown mode z z z z z fixed 500khz frequency z z z z z thermal shutdown z z z z z cycle-by-cycle over current protection z z z z z wide 5.5v to 36v operating input range z z z z z adjustable output voltage from 1.222v to 26v z z z z z available in an sop8 (exposed pad) package z z z z z rohs compliant and halogen free RT8279 gspymdnn marking information RT8279gsp : product number ymdnn : date code package type sp : sop-8 (exposed pad-option 1) RT8279 lead plating system g : green (halogen free and pb free)
RT8279 2 ds8279-01 december 2011 www.richtek.com functional pin description pin no. pin name pin function 1 boot high side gate drive boost input. boot supplies the drive for the high side n-mosfet switch. connect a 10nf or greater capacitor from sw to boot to power the high side switch. 2, 3 nc no internal connection. 4 fb feedback input. the feedback threshold is 1.222v. 5 en enable input. en is a digital input that turns the regulator on or off. drive en higher than 1.4v to turn on the regulator, lower than 0.4v to turn it off. for automatic startup, leave en unconnected. 6, 9 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 7 vin power input. a suitable large capacitor should be bypassed from vin to gnd to eliminate noise on the input to the ic. 8 sw power switching output. note that a capacitor is required from sw to boot to power the high side switch. typical application circuit table 1. recommended component selection v out (v) r1 (k ) r2 (k ) c ff (pf) l ( h) c out ( f) 2.5 100 100 82 6.8 22 x 2 3.3 100 58.6 82 10 22 x 2 5 100 31.6 82 15 22 x 2 8 100 18 82 22 22 x 2 vin en gnd boot fb sw 5 4 7 8 1 l1 10nf 22f x 2 r1 r2 v out 4.7f/ 50v x 2 chip enable v in 5.5v to 36v RT8279 d1 b550a 6, 9 (exposed pad) c boot c out c in open = automatic startup c ff
RT8279 3 ds8279-01 december 2011 www.richtek.com function block diagram s q r driver bootstrap control - + current sense amplifier pwm comparator oscillator 500khz ramp generator regulator reference + - 12k error amplifier 30pf 400k 13pf sw boot fb en vin gnd + -
RT8279 4 ds8279-01 december 2011 www.richtek.com absolute maximum ratings (note 1) z supply voltage, v in ------------------------------------------------------------------------------------------ ? 0.3v to 40v z switching voltage, sw ------------------------------------------------------------------------------------- ? 0.3v to v in + 0.3v z boot v oltage ------------------------------------------------------------------------------------------------- (v sw ? 0.3v) to (v sw + 6v) z the other pins ------------------------------------------------------------------------------------------------ ? 0.3v to 6v z power dissipation, p d @ t a = 25 c sop-8 (exposed pad) -------------------------------------------------------------------------------------- 1.333w z package thermal resistance (note 2) sop-8 (exposed pad), ja --------------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc -------------------------------------------------------------------------------- 15 c/w z junction temperature ---------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------ 260 c z storage temperature range ------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) --------------------------------------------------------------------------------- 2kv mm (ma chine mode) ----------------------------------------------------------------------------------------- 200v recommended operating conditions (note 4) z supply voltage, v in ------------------------------------------------------------------------------------------ 5.5v to 36v z junction temperature range ------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics parameter symbol test conditions min typ max unit reference voltage v ref 5.5v v in 36v 1.202 1.222 1.239 v high side switch-on resistance r ds(on)1 -- 110 160 m low side switch-on resistance r ds(on)2 -- 10 15 high side switch leakage v en = 0v, v sw = 0v -- -- 10 a current limit i lim duty = 90%, v boot ? sw = 4.8v 6 7.5 9 a oscillator frequency f osc 425 500 575 khz short circuit frequency v fb = 0v -- 150 -- khz maximum duty cycle d max v fb = 0.8v 85 90 95 % minimum on-time t on -- 100 150 ns under voltage lockout threshold rising 3.8 4.2 4.5 v under voltage lockout threshold hysteresis -- 315 -- mv logic-high v ih en_hys = 350mv 1.4 -- -- en threshold voltage logic-low v il -- -- 0.4 v enable pull up current -- 1 -- a shutdown current i shdn v en = 0v -- 25 45 a quiescent current i q v en = 2v, v fb = 1.5v -- 0.6 1 ma soft-start period c ss = 0.1 f 3 5 8.2 ms thermal shutdown t sd -- 150 -- c (v in = 12v, t a = 25 c unless otherwise specified)
RT8279 5 ds8279-01 december 2011 www.richtek.com note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8279 6 ds8279-01 december 2011 www.richtek.com typical operating characteristics frequency vs. temperature 440 450 460 470 480 490 500 510 520 530 540 -50 -25 0 25 50 75 100 125 temperature (c) frequency (khz ) v out = 5v v in = 12v v in = 24v v in = 36v frequency vs. input voltage 440 450 460 470 480 490 500 510 520 530 540 4 8 12 16 20 24 28 32 36 input voltage (v) frequency (khz ) v out = 5v, i out = 0a reference voltage vs. temperature 1.210 1.212 1.214 1.216 1.218 1.220 1.222 1.224 1.226 1.228 1.230 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) i out = 0a v in = 12v v in = 24v v in = 36v output voltage vs. output current 4.960 4.964 4.968 4.972 4.976 4.980 4.984 4.988 4.992 4.996 5.000 5.004 5.008 012345 output current (a) output voltage (v) v out = 5v v in = 36v v in = 24v v in = 12v reference voltage vs. input voltage 1.210 1.214 1.218 1.222 1.226 1.230 4 8 12 16 20 24 28 32 36 input voltage (v) reference voltage (v) v out = 5v, i out = 0a efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 012345 output current (a) efficiency (%) v out = 5v v in = 12v v in = 32v v in = 36v
RT8279 7 ds8279-01 december 2011 www.richtek.com current limit vs. temperature 5 6 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature (c) current limit (a) v in = 12v shutdown current vs. input voltage 0 10 20 30 40 50 60 4 8 12 16 20 24 28 32 36 input voltage (v) shutdown current ( a ) v en = 0v quiescent current vs. temperature 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -50 -25 0 25 50 75 100 125 temperature (c) quiescent current (ma) v in = 36v v in = 24v v in = 12v load transient response time (100 s/div) v out (200mv/div) i out (2a/div) v in = 12v, v out = 5v, i out = 0.2a to 5a load transient response time (100 s/div) v out (200mv/div) i out (2a/div) v in = 12v, v out = 5v, i out = 2.5a to 5a switching time (1 s/div) v out (10mv/div) i l (5a/div) v in = 12v, v out = 5v, i out = 5a v sw (10v/div)
RT8279 8 ds8279-01 december 2011 www.richtek.com power off from en time (2.5ms/div) v en (5v/div) i l (5a/div) v in = 12v, v out = 5v, i out = 5a v out (5v/div) power on from en time (2.5ms/div) v en (5v/div) i l (5a/div) v in = 12v, v out = 5v, i out = 5a v out (5v/div)
RT8279 9 ds8279-01 december 2011 www.richtek.com application information the RT8279 is an asynchronous high voltage buck converter that can support the input voltage range from 5.5v to 32v and the output current can be up to 5a. output voltage setting the resistive divider allows the fb pin to sense the output voltage as shown in figure 1. figure 1. output voltage setting the output voltage is set by an external resistive divider according to the following equation : out ref r1 v = v 1 r2 ?? + ?? ?? where v ref is the reference voltage (1.222v typ.). where r1 = 100k . external bootstrap diode connect a 10nf low esr ceramic capacitor between the boot pin and sw pin. this capacitor provides the gate driver voltage for the high side mosfet. it is recommended to add an external bootstrap diode between an external 5v and boot pin for efficiency improvement when input voltage is lower than 5.5v or duty ratio is higher than 65% .the bootstrap diode can be a low cost one such as in4148 or bat54. the external 5v can be a 5v fixed input from system or a 5v output of the RT8279. figure 2. external bootstrap diode soft-start the RT8279 contains an internal soft-start clamp that gradually raises the output voltage. the typical soft-start t ime is 5ms. chip enable operation the en pin is the chip enable input. pull the en pin low (<0.4v) will shutdown the device. during shutdown mode, the RT8279 quiescent current drops to lower than 25 a. drive the en pin to high (>1.4v, <5.5v) will turn on the device again. if the en pin is open, it will be pulled to high by internal circuit. for external timing control (e.g.rc),the en pin can also be externally pulled to high by adding a 100k or greater resistor from the vin pin (see figure 3 ). inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. high frequency with small ripple current can achieve highest efficiency operation. however, it requires a large inductor to achieve this goal. for the ripple current selection, the val ue of i l = 0.2(i max ) will be a reasonable starting point. the large st ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? the inductor's current rating (caused a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. please see table 2 for the inductor selection reference. RT8279 gnd fb r1 r2 v out sw boot 5v RT8279 10nf
RT8279 10 ds8279-01 december 2011 www.richtek.com checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr) also begins to charge or discharge c out generating a feedback error signal for the regulator to return v out to its steady-state value. during this out in rms out(max) in out v v i = i 1 vv ? out l out 1 viesr 8fc ?? ?? + ?? ?? the output ripple will be highest at the maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirement. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr value. however, it provides lower capacitance density than other types. although tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr. however, it can be used in cost-sensitive applications for ripple current rating and long term reliability considerations. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. diode selection when the power switch turns off, the path for the current is through the diode connected between the switch output and ground. this forward biased diode must have a minimum voltage drop and recovery times. schottky diode is recommended and it should be able to handle those current. the reverse voltage rating of the diode should be greater than the maximum input voltage, and current rating should be greater than the maximum load current. for more detail please refer to table 4. c in and c out selection the input capacitance, c in, is needed to filter the trapezoidal current at the source of the high side mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the rms current is given by : table 2. suggested inductors for typical application circuit component supplier series dimensions (mm) taiyo yuden nr10050 10 x 9.8 x 5 tdk slf12565 12.5 x 12.5 x 6.5 the output ripple, v out , is determined by : this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for the input capacitor, two 4.7 f low esr ceramic capacitors are recommended. for the recommended capacitor, please refer to table 3 for more detail. the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section.
RT8279 11 ds8279-01 december 2011 www.richtek.com figure 3. reference circuit with snubber and enable timing control recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. emi consideration since parasitic inductance and capacitance effects in pcb circuitry w ould cause a spike voltage on sw pin when high side mosfet is turned-on /off, this spike voltage on sw may impact on emi performance in the system. in order to enhance emi performance, there are two methods to suppress the spike voltage. one is to place an r-c snubber between sw and gnd and make them as close as possible to the sw pin (see figure 3). another method is to add a resistor in series with the bootstrap capacitor, c boot . but this method will decrease the driving capability to the high side mosfet. it is strongly recommended to reserve the r-c snubber during pcb layout for emi improvement. moreover, reducing the sw trace area and keeping the main power in a small loop will be helpful on emi performance. for detailed pcb layout guide, please refer to the section of layout consideration. thermal considerations for continuous operation, do not exceed the maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature , t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8279, the maximum junction temperature is 125 c . the junction to ambient thermal resistance ja is layout dependent. for psop-8 package, the thermal resistance ja is 75 c /w on the standard jedec 51-7 four-layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c ) / (75 c /w) = 1.333w (min.copper area pcb layout) p d(max) = (125 c ? 25 c ) / (49 c /w) = 2.04w (70mm 2 copper area pcb layout) the thermal resistance ja of sop-8 (exposed pad) is determined by the package architecture design and the pcb layout design. however, the package architecture design had been designed. if possible, it's useful to increase thermal performance by the pcb layout copper design. the thermal resistance ja can be decreased by adding copper area under the exposed pad of sop-8 (ex posed pad) package. as shown in figure 4, the amount of copper area to which the sop-8 (exposed pad) is mounted affects thermal performance. when mounted to the standard sop-8 (exposed pad) pad (figure 4a), ja is 75 c/w. adding copper area of pad under the sop-8 (exposed pad) (figure 4.b) reduces the ja to 64 c/w. even further, increasing the copper area of pad to 70mm 2 (figure 4.e) reduces the ja to 49 c/w. vin en gnd boot fb sw 5 4 7 8 1 l 10h 10nf r1 10k r2 3.16k v out 5v/5a 4.7f x 2 v in 5.5v to 32v RT8279 d b550c 6, 9 (exposed pad) c boot c out c in r boot * r s * c s * r en * c en * * : optional 47fx2 (poscap)
RT8279 12 ds8279-01 december 2011 www.richtek.com layout consideration follow the pcb layout guidelines for optimal performance of the RT8279. ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` sw node is with high frequency voltage swing and should be kept at small area. keep analog components away from the sw node to prevent stray capacitive noise pick- up. ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the RT8279. ` connect all analog grounds to a common node and then connect the common node to the power ground behind the output capacitors. ` an example of pcb layout guide is shown in figure 6 for reference. (a) copper area = (2.3 x 2.3) mm 2 , ja = 75 c/w (b) copper area = 10mm 2 , ja = 64 c/w (c) copper area = 30mm 2 , ja = 54 c/w (d) copper area = 50mm 2 , ja = 51 c/w (e) copper area = 70mm 2 , ja = 49 c/w figure 4. thermal resistance vs. copper area layout design figure 5. derating curves for RT8279 package the maximum power dissipation depends on operating ambient temperature for fixed t j (max) and thermal resistance ja . for the RT8279, the figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 25 50 75 100 125 ambient temperature (c) power dissipation (w) copper area 70mm 2 50mm 2 30mm 2 10mm 2 min.layout four layer pcb
RT8279 13 ds8279-01 december 2011 www.richtek.com figure 6. pcb layout guide table 3. suggested capacitors for c in and c out component supplier series v rrm (v) i out (a) package diodes b550c 50 5 smc panjit sk55 50 5 smc table 4. suggested diode location component supplier part no. capacitance ( f) case size c in murata grm32er71h475k 4.7 1206 c in taiyo yuden umk325bj475mm-t 4.7 1206 c out murata grm31cr60j476m 47 1206 c out tdk c3225x5r0j476m 47 1210 c out murata grm32er71c226m 22 1210 c out tdk c3225x5r1c22m 22 1210 boot nc nc fb sw vin en gnd gnd 2 3 4 5 6 7 8 9 c in v out gnd v out r1 r2 sw c boot d1 the feedback components should be connected as close to the device as possible. sw should be connecte d to inductor by wide and short trace. keep sensitive components away from this trace. l1 c out c in c out input capacitor should be placed as close to the ic as possible.
RT8279 14 ds8279-01 december 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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